@IEEEtranBSTCTL{bstctl:etal,
  CTLuse_forced_etal = {no},
  CTLmax_names_forced_etal = {3},
}

@IEEEtranBSTCTL{bstctl:nodash,
  CTLdash_repeated_names = {no},
}

@IEEEtranBSTCTL{bstctl:simpurl,
  CTLname_url_prefix = {Available: },
}




@INPROCEEDINGS{islped11,
  author={Swaminathan, K. and Kultursay, E. and Saripalli, V. and Narayanan, V. and Kandemir, M.T. and Datta, S.}, 
  booktitle={ISLPED}, 
  title={Improving energy efficiency of multi-threaded applications using heterogeneous {CMOS-TFET} multicores}, 
  year={2011}
}


@inproceedings{codes12,
 author = {Kultursay, E. and Swaminathan, K. and Saripalli, V. and Narayanan, V. and Kandemir, M.T. and Datta, S.},
 title = {Performance enhancement under power constraints using heterogeneous {CMOS-TFET} multicores},
 booktitle = {CODES+ISSS},
 year = {2012}
} 

@INPROCEEDINGS{steepslope, 
  author={Lu, Z. and others}, 
  booktitle={IEDM}, 
  title={Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages}, 
  year={Dec.} 
}


@INPROCEEDINGS{sram8t,
  author={Chang, L. and others}, 
  booktitle={VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on}, 
  title={Stable {SRAM} cell design for the 32 nm node and beyond}, 
  year={June} 
}

@inproceedings{corefusion,
 author = {Ipek, E. and Kirman, M.  and Kirman, N. and Martinez, J. F.},
 title = {Core fusion: accommodating software diversity in chip multiprocessors},
 booktitle = {Proceedings of the 34th annual international symposium on Computer architecture},
 year = {2007}
} 

@ARTICLE{asymmetric, 
  author={Kumar, R. and Tullsen, D.M. and Jouppi, N.P. and Ranganathan, P.}, 
  journal={Computer}, 
  title={Heterogeneous chip multiprocessors}, 
  year={Nov.}
}

%TFET papers

@inproceedings{mookerjea,
  author={S. Mookerjea and others},
  title={{Experimental Demonstration of 100nm Channel Length {In0.53Ga0.47As}-based Vertical Inter-band Tunnel Field Effect Transistors ({TFETs}) for Ultra Low-Power Logic and {SRAM} Applications}},
  booktitle={IEDM},
  year={2009}
}



@ARTICLE{seabaugh, 
  author={Seabaugh, A. C. and Zhang, Q. }, 
  journal={Proceedings of the IEEE}, 
  title={Low-Voltage Tunnel Transistors for Beyond CMOS Logic}, 
  year={Dec.}
}



@article{salahuddin,
  author = {Salahuddin, S. and Datta, S. },
  title = {Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices},
  journal = {Nano Letters},
  year = {2008}
}


@inproceedings{taylor-dac2012,
 author = {Taylor, M. B.},
 title = {Is dark silicon useful?: {H}arnessing the four horsemen of the coming dark silicon'apocalypse},
 booktitle = {DAC},
 year = {2012},
} 

@inproceedings{dac11,
  author = { Saripalli, V. and others},
  title = {{An Energy-Efficient Heterogeneous {CMP} based on Hybrid {TFET-CMOS} cores}},
  booktitle ={DAC},
  year = {2011}
}


@inproceedings{slack,
 author = {Fields, B. and Bod\'{\i}k, R. and Hill, M. D.},
 title = {Slack: maximizing performance under technological constraints},
 booktitle = {ISCA},
 series = {ISCA '02},
 year = {2002}
}


@inproceedings{morphcore,
 author = {Khubaib and M. Aater Suleman and Milad Hashemi and Chris Wilkerson and Yale N. Patt},
 title = {MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP},
 booktitle = {MICRO},
 year = {2012}
} 

@ARTICLE{NTC-UMich,
author={Dreslinski, R.G. and Michael Wieckowski and David Blaauw and Dennis Sylvester and Trevor Mudge},
journal={Proceedings of the IEEE},
title={{Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits}},
year={2010}
}

@inproceedings{aergia,
    author = {Das, R. and others},
    title = {Aergia: Exploiting Packet Latency Slack in On-Chip Networks},
    booktitle ={ISCA},
    year = {2010}
}

@inproceedings{asit-sttram,
 author = {Mishra, A. K. and others},
 title = {Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs},
 booktitle = {ISCA},
 series = {ISCA '11},
 year = {2011}
} 


@INPROCEEDINGS{iedm11, 
author={Mohata, D.K. and others}, 
booktitle={IEDM}, 
title={Demonstration of {MOSFET-like on-current performance in arsenide/antimonide tunnel FETs} with staggered hetero-junctions for 300mV logic applications}, 
year={2011}
}

@INPROCEEDINGS{iedm09, 
author={Mookerjea, S. and others}, 
booktitle={IEDM}, 
title={{Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications}}, 
year={2009}
}


@misc{intel-gargini,
      title  = "{Intel's Gargini sees tunnel FET as transistor option}",
      author = "Peter Clarke",
      booktitle = "EETimes",
      year   = "2011"
    }


@misc{arm-muller,
      title  = "{ARM CTO warns of Dark Silicon}",
      author = "John Donovan",
      booktitle = "EETimes",
      year   = "2010"
    }

@inproceedings{micro03,
 author = {Kumar, R. and Farkas, K.I. and Jouppi, N.P. and Ranganathan, P. },
 title = {Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction},
 booktitle = {MICRO},
 series = {MICRO 36},
 year = {2003}
}

// Asymmetric CMPs
@inproceedings{isca04,
 author = {Kumar, R. and Tullsen, D. and Ranganathan, P. and Jouppi, N. and Farkas, K},
 title = {Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance},
 booktitle = {ISCA},
 year = {2004}
}

@INPROCEEDINGS{Proactivetemp,
 author={Coskun, A.K and others},
 title={Proactive Temperature Management in MPSoCs},
 booktitle={ISLPED}, 
 year={2011}
}

@article{prometheus,
 author = {Sharifi, S. and others},
 title = {PROMETHEUS: A Proactive Method for Thermal Management of Heterogeneous {MPSoCs}},
 journal = {TCAD},
 year = {2013}
}


@INPROCEEDINGS{ekman-icpp03, 
author={Ekman, M. and Stenstrom, P.}, 
booktitle={Parallel Processing, 2003. Proceedings. 2003 International Conference on}, 
title={Performance and power impact of issue-width in chip-multiprocessor cores}, 
year={2003}
}


@INPROCEEDINGS{vlsit-dhiraj, 
author={Mohata, D.K. and others}, 
booktitle={VLSI Technology (VLSIT)}, 
title={Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio}, 
year={2012}
}

@INPROCEEDINGS{avci-vlsit, 
author={Avci, U.E. and others}, 
booktitle={VLSI Technology (VLSIT)}, 
title={Understanding the feasibility of scaled III-V TFET for logic by bridging atomistic simulations and experimental results}, 
year={2012}
}


@ARTICLE{vinay-jetcas11, 
author={Saripalli, V. and others}, 
journal={Emerging and Selected Topics in Circuits and Systems, IEEE Journal on}, 
title={Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors}, 
year={2011}
}


@ARTICLE{millercap, 
author={Mookerjea, S. and others}, 
journal={Electron Device Letters, IEEE}, 
title={On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors}, 
year={2009}
}



@ARTICLE{iedm12, 
author={Liu, L. and others}, 
journal={Electron Devices, IEEE Trans.}, 
title={Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors}, 
year={2012}
}


@INPROCEEDINGS{mcpat, 
author={Li, S. and others}, 
booktitle={MICRO}, 
title={{McPAT}: An integrated power, area, and timing modeling framework for multicore and manycore architectures}, 
year={2009}
}


@INPROCEEDINGS{hotspot,
    author = {Huang, W. and others},
    title = {Accurate Pre-{RTL} Temperature-Aware Design Using a Parameterized, Geometric Thermal Model},
    booktitle = {ISSCC},
    year = {2008}
}



@misc{tcad-sentaurus,
      title  = "{TCAD Sentaurus Device Manual}",
      author = "",
      booktitle = "Synopsis",
      year   = "2010"
   }


@inproceedings{ parsec,
  author = {Bienia, C. and Li, K},
  title = {{PARSEC 2.0}: A New Benchmark Suite for Chip-Multiprocessors},
  booktitle = {Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation},
  year = {2009}}
}


@article{gems,
 author = {Martin, M.K. and others},
 title = {Multifacet's general execution-driven multiprocessor simulator ({GEMS}) toolset},
 journal = {SIGARCH Comput. Archit. News},
 year = {2005} 
}


@INPROCEEDINGS{HuichuIEDM2012, 
author={Liu, H. and others}, 
booktitle={IEDM}, 
title={Technology assessment of {Si} and {III-V} {FinFETs} and {III-V} tunnel {FETs} from soft error rate perspective}, 
year={2012}
}

@inproceedings{conservation-cores,
 author = {Venkatesh, G. and others},
 title = {Conservation cores: reducing the energy of mature computations},
 booktitle = {ASPLOS},
 year = {2010}
}
 
@ARTICLE{king-end-cmos-scaling,
author={Skotnicki, T. and others},
journal={IEEE Circuits and Devices Magazine},
title={{The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance}},
year={2005}
}


@INPROCEEDINGS{isqed05, 
author={Link, G.M. others}, 
booktitle={Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on}, 
title={Thermal trends in emerging technologies}, 
year={2006}
}


@inproceedings{slack-tullsen,
 author = {Seng, John S. and others},
 title = {Reducing power with dynamic critical path information},
 booktitle = {MICRO},
 series = {MICRO 34},
 year = {2001}
}

@INPROCEEDINGS{slack-zhang, 
author={Zhang, W. and others}, 
booktitle={Design, Automation and Test in Europe Conference and Exhibition, 2003}, 
title={Compiler support for reducing leakage energy consumption}, 
year={2003}
}


@inproceedings{isca11-darksilicon,
   author={Esmaeilzadeh, H. and Blem, E. and St.Amant, R. and Sankaralingam, K. and Burger, D.},
   title={{Dark Silicon and the End of Multicore Scaling}},
   booktitle="{Proceedings of the 38th International Symposium on Computer Architecture (ISCA)}",
   year={2011}
 }

@inproceedings{venkatesh2010conservation,
author = {Venkatesh, G. and others},
 title = {Conservation cores: reducing the energy of mature computations},
 booktitle = {Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems},
 series = {ASPLOS XV},
 year = {2010},
 isbn = {978-1-60558-839-1},
 location = {Pittsburgh, Pennsylvania, USA},
 pages = {205--218},
 numpages = {14},
 url = {http://doi.acm.org/10.1145/1736020.1736044},
 doi = {10.1145/1736020.1736044},
 acmid = {1736044},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {conservation core, heterogeneous many-core, patching, utilization wall},
} 



@ARTICLE{kmeans, 
author={Lloyd, S.}, 
journal={Information Theory, IEEE Transactions on}, 
title={Least squares quantization in PCM}, 
year={1982}}


@misc{digitalversus-samsung,
      title  = "{Samsung Galaxy S II: Clock Rate and Temperature Differences}",
      author = "Vincent Alzieu ",
      booktitle = "Digital Versus",
      year   = "2012"
    }

@misc{pcworld-laptop,
      title  = "{Free Utility Core Temp Tells You If Your CPU Is Overheating}",
      author = "Erez Zukerman",
      booktitle = "PCWorld",
      year   = "2011"
    }






@ARTICLE{thermal-dvfs-asu, 
author={Hanumaiah, V. and Vrudhula, S.}, 
journal={Computers, IEEE Transactions on}, 
title={Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors}, 
year={2012}, 
volume={61}, 
number={10}, 
pages={1484-1494}, 
doi={10.1109/TC.2011.156}, 
ISSN={0018-9340},
}


@INPROCEEDINGS{ionescu-3D, 
author={Fernandez-Bolanos, M. and Ionescu, A.M.}, 
booktitle={3D Systems Integration Conference (3DIC), 2010 IEEE International}, 
title={{3D} heterogeneous integration for novel functionality}, 
year={2010}, 
pages={1-19}, 
doi={10.1109/3DIC.2010.5751423}
}

@INPROCEEDINGS{ionescu-nems, 
author={Ionescu, A.-M. and others}, 
booktitle={Electron Devices Meeting (IEDM), 2011 IEEE International}, 
title={Ultra low power: Emerging devices and their benefits for integrated circuits}, 
year={2011}, 
pages={16.1.1-16.1.4}, 
doi={10.1109/IEDM.2011.6131563}, 
ISSN={0163-1918},
}


@INPROCEEDINGS{tullsen-3D, 
author={Homayoun, H. and Kontorinis, V. and Shayan, A. and Ta-Wei Lin and Tullsen, D.M.}, 
booktitle={High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on}, 
title={Dynamically heterogeneous cores through 3D resource pooling}, 
year={2012}, 
pages={1-12}, 
doi={10.1109/HPCA.2012.6169037}, 
ISSN={1530-0897},}


@ARTICLE{ieeemicro-sprinting, 
author={Raghavan, A. and others}, 
journal={Micro, IEEE}, 
title={Utilizing Dark Silicon to Save Energy with Computational Sprinting}, 
year={2013}, 
volume={33}, 
number={5}, 
pages={20-28}, 
doi={10.1109/MM.2013.76}, 
ISSN={0272-1732},
}

@ARTICLE{ieeemicro-tfet, 
author={Swaminathan, K. and others}, 
journal={Micro, IEEE}, 
title={Steep-Slope Devices: From Dark to Dim Silicon}, 
year={2013}, 
volume={33}, 
number={5}, 
pages={50-59}, 
keywords={CMOS integrated circuits;microprocessor chips;multiprocessing systems;power aware computing;CMOS technology;device-level heterogeneous multicores;energy efficiency;resource-management schemes;sequential applications;smart resource management;steep-slope devices;subthreshold characteristics;CMOS integrated circuits;Dynamic scheduling;Low voltage;Multicore processing;Performance evaluation;Program processors;Semiconductor device manufacture;Silicon;CMOS-TFET heterogeneous architectures;DVFS;dark silicon;dim silicon;dynamic voltage and frequency scaling;power partitioning;steep-slope devices;thread migration}, 
doi={10.1109/MM.2013.75}, 
ISSN={0272-1732},
}

@ARTICLE{Dennard1974, 
author={Dennard, R.H. and others}, 
journal={Solid-State Circuits, IEEE Journal of}, 
title={Design of ion-implanted MOSFET's with very small physical dimensions}, 
year={1974}, 
volume={9}, 
number={5}, 
pages={256-268}, 
keywords={Digital integrated circuits;Field effect transistors;Ion implantation;Semiconductor device manufacture;Switching circuits;digital integrated circuits;field effect transistors;ion implantation;semiconductor device manufacture;switching circuits;Digital integrated circuits;Doping profiles;Fabrication;Ion implantation;Length measurement;MOSFET circuits;Predictive models;Semiconductor process modeling;Switching circuits;Threshold voltage}, 
doi={10.1109/JSSC.1974.1050511}, 
ISSN={0018-9200},}

@inproceedings{hhlee-3D-dvfs,
 author = {Choi, Hong Jun and Park, Young Jin and Lee, Hsien-Hsin and Kim, Cheol Hong},
 title = {Adaptive Dynamic Frequency Scaling for Thermal-aware 3D Multi-core Processors},
 booktitle = {Proceedings of the 12th International Conference on Computational Science and Its Applications - Volume Part IV},
 series = {ICCSA'12},
 year = {2012},
 isbn = {978-3-642-31127-7},
 location = {Salvador de Bahia, Brazil},
 pages = {602--612},
 numpages = {11},
 url = {http://dx.doi.org/10.1007/978-3-642-31128-4_44},
 doi = {10.1007/978-3-642-31128-4_44},
 acmid = {2346389},
 publisher = {Springer-Verlag},
 address = {Berlin, Heidelberg},
 keywords = {3D integration technology, dynamic frequency scaling, multi-core processor, processor architecture, thermal management},
}

@INPROCEEDINGS{yibo-yield-iccad, 
author={Yibo Chen and Dimin Niu and Yuan Xie and Chakrabarty, K}, 
booktitle={ICCAD}, 
title={{Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis}}, 
year={2010}, 
pages={471-476}, 
doi={10.1109/ICCAD.2010.5653753}, 
ISSN={1092-3152},} 


@INPROCEEDINGS{microfluidic-cooling, 
author={Zhang, Y. and Dembla, A. and Joshi, Y. and Bakir, M.S.}, 
booktitle={Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd}, 
title={{3D stacked microfluidic cooling for high-performance 3D ICs}}, 
year={2012}, 
pages={1644-1650}, 
doi={10.1109/ECTC.2012.6249058}, 
ISSN={0569-5503},}

@ARTICLE{ieeemicro-llano, 
author={Branover, A. and Foley, D. and Steinman, M.}, 
journal={Micro, IEEE}, 
title={AMD Fusion APU: Llano}, 
year={2012}, 
volume={32}, 
number={2}, 
pages={28-37}, 
doi={10.1109/MM.2012.2}, 
ISSN={0272-1732},}

@inproceedings{hotspot3d,
 author = {Jie, M. and Kawakami, K. and Coskun, A.K.},
 title = {Optimizing Energy Efficiency of {3-D multicore systems with stacked DRAM} Under Power and Thermal Constraints},
 booktitle = {Proceedings of the 49th Annual Design Automation Conference},
 year = {2012},
 isbn = {978-1-4503-1199-1},
 location = {San Francisco, California},
 pages = {648--655},
 numpages = {8},
 url = {http://doi.acm.org/10.1145/2228360.2228477},
 doi = {10.1145/2228360.2228477},
 acmid = {2228477},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {3D multicore system, energy efficiency, thermal management},
}

@misc{itrs2011,
      title  = {The International Technology Roadmap for Semiconductors {(ITRS)}},
      author = "ITRS",
      booktitle = "System Drivers",
      year   = "2011"
   }
 
@INPROCEEDINGS{sniper, 
author={Carlson, T.E. and Heirman, W. and Eeckhout, L.}, 
booktitle={High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for}, 
title={Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation}, 
year={2011}, 
pages={1-12}, 
keywords={cache storage;digital simulation;multiprocessing systems;16-core system;8-core SMP machine;Sniper;abstraction level exploration;core larger numbers;core-uncore interactions;cycle-accurate simulation;hardware design space;high-performance computing;interval simulation;multithreaded workloads;on-chip cache memory;one-IPC simulation;parallel multicore simulation;processor architectures;Accuracy;Analytical models;Kernel;Load modeling;Multicore processing;Synchronization;Interval simulation;interval model;multi-core processor;performance modeling},}


@ARTICLE{Lu-tfet-scaling, 
author={Lu Liu and Mohata, D. and Datta, S.}, 
journal={Electron Devices, IEEE Transactions on}, 
title={Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors}, 
year={2012}, 
volume={59}, 
number={4}, 
pages={902-908}, 
keywords={Green's function methods;insulated gate field effect transistors;tunnel transistors;atomistic nonequilibrium Green function simulation;band-to-band tunneling generation rate;commercial simulator;double-gate interband tunnel field-effect transistor;electrostatic potential profile;electrostatic scaling length;heterojunction TFET;homojunction TFET;physics-based 2D analytical model;scaling length theory;short-channel performance;Analytical models;Electric potential;Electrostatics;Heterojunctions;Logic gates;MOSFETs;Tunneling;Analytical model;drain-induced barrier lowering (DIBL);drain-induced barrier thinning (DIBT);scalability;short-channel effect;tunnel field-effect transistor (TFET)}, 
doi={10.1109/TED.2012.2183875}, 
ISSN={0018-9383},}


@INPROCEEDINGS{emma-3d, 
author={Emma, P. and others}, 
booktitle={High Performance Computer Architecture (HPCA) Industry Session, 2014 IEEE 20th International Symposium on}, 
title={{3D} stacking of High Performance Processors}, 
year={2014}, 
pages={1-12}, 
ISSN={1530-0897},}

@INPROCEEDINGS{tfet-sram, 
author={Saripalli, V. and Datta, S. and Narayanan, V. and Kulkarni, J.P.}, 
booktitle={Nanoscale Architectures (NANOARCH), International Symposium on}, 
title={Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design}, 
year={2011}, 
pages={45-52}, 
keywords={CMOS integrated circuits;SRAM chips;field effect transistors;low-power electronics;power aware computing;trigger circuits;Schmitt-Trigger feedback mechanism;low supply voltage applications;uni-directional conduction;variation-tolerant ultra low-power heterojunction tunnel FET SRAM design;voltage 124 mV;CMOS integrated circuits;FinFETs;Logic gates;Noise;Random access memory;Silicon}, 
doi={10.1109/NANOARCH.2011.5941482},}

@INPROCEEDINGS{tfet-intel, 
author={Dewey, G. and others}, 
booktitle={Electron Devices Meeting (IEDM), 2011 IEEE International}, 
title={Fabrication, characterization, and physics of {III-V} heterojunction tunneling Field Effect Transistors {(H-TFET)} for steep sub-threshold swing}, 
year={2011}, 
pages={33.6.1-33.6.4}, 
keywords={III-V semiconductors;field effect transistors;semiconductor doping;semiconductor heterojunctions;tunnel transistors;H-TFET;III-V heterojunction tunneling field effect transistors;drain current;drive current;electrical oxide thickness scaling;heterojunction engineering;source doping;source-to-channel tunnel barrier height;steep subthreshold swing;thin gate oxide;Doping;Gate leakage;HEMTs;Heterojunctions;Indium gallium arsenide;Logic gates}, 
doi={10.1109/IEDM.2011.6131666}, 
ISSN={0163-1918},}


@inproceedings{reetu-3d-cost,
 author = {Wu, X. and others},
 title = {Cost-driven {3D} Integration with Interconnect Layers},
 booktitle = {Design Automation Conference (DAC)},
 year = {2010},
 isbn = {978-1-4503-0002-5},
 location = {Anaheim, California},
 pages = {150--155},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/1837274.1837313},
 doi = {10.1145/1837274.1837313},
 acmid = {1837313},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {interconnect service layer, network-on-chip, three-dimensional integrated circuit},
} 

@INPROCEEDINGS{SolomonDRC2011, 
author={Solomon, P.M. and Frank, D.J. and Koswatta, S.O.}, 
booktitle={Device Research Conference (DRC), 2011 69th Annual}, 
title={Compact model and performance estimation for tunneling nanowire {FET}}, 
year={2011}, 
month={June}, 
pages={197-198}, 
keywords={field effect transistors;nanowires;tunnelling;TFET;circuit simulation;compact model;multiparameter optimization;performance estimation;tunneling nanowire FET;Capacitance;Clocks;Delay;Integrated circuit modeling;Logic gates;Switches;Tunneling}, 
doi={10.1109/DRC.2011.5994495}, 
ISSN={1548-3770},}

@ARTICLE{VerhulstAPL2011, 
author={Verhulst, A.S. and Leonelli, D. and Rooyackers, R. and Groeseneken, G.}, 
journal={Journal of Applied Physics}, 
title={Drain voltage dependent analytical model of tunnel field-effect transistors}, 
year={2011}, 
month={Jul}, 
volume={110}, 
number={2}, 
pages={024510-024510-10}, 
doi={10.1063/1.3609064}, 
ISSN={0021-8979},}

@ARTICLE{seoane-workfunction, 
author={Seoane, N. and others}, 
journal={Electron Devices, IEEE Transactions on}, 
title={Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a  Nano {InGaAs FinFET}}, 
year={2014}, 
month={June}, 
}

@ARTICLE{FanTED2013, 
author={Fan, M-L and Hu, V.P.-H. and Chen, Y-N and Su, P. and Chuang, C-T}, 
journal={Electron Devices, IEEE Transactions on}, 
title={Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel {FET}}, 
year={2013}, 
month={June}, 
volume={60}, 
number={6}, 
pages={2038-2044}, 
doi={10.1109/TED.2013.2258157}, 
ISSN={0018-9383},}


@INPROCEEDINGS{HuichuISLPED2013Rectifier, 
author={Liu, H. and Vaddi, R. and Datta, S. and Narayanan, V.}, 
booktitle={Low Power Electronic Design (ISLPED), International Symposium on}, 
title={{Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier}}, 
year={2013}, 
doi={10.1109/ISLPED.2013.6629287}}

@ARTICLE{WanAPL2010, 
author={Wan, J. and Le Royer, C. and Zaslavsky, A. and Cristoloveanu, S.}, 
journal={Applied Physics Letters}, 
title={Low-frequency noise behavior of tunneling field effect transistors}, 
year={2010}, 
volume={97}, 
number={24}, 
pages={243503-243503-3}, 
doi={10.1063/1.3526722}, 
ISSN={0003-6951},}

@INPROCEEDINGS{BijeshDRC2012, 
author={Rajamohan, B. and Mohata, D.K. and Liu, H. and Datta, S.}, 
booktitle={Device Research Conference (DRC), 2012 70th Annual}, 
title={Flicker noise characterization and analytical modeling of homo and hetero-junction {III-V tunnel FETs}}, 
year={2012}, 
month={June}, 
keywords={field effect transistors;flicker noise;semiconductor device models;tunnelling;TFET;analytical modeling;band-to-band tunneling;flicker noise;hetero-junction III-V tunnel FET;homo-junction III-V tunnel FET;temperature 300 K;temperature dependent transfer;trap assisted tunneling;voltage 500 mV;FETs;Logic gates;Noise;Substrates}, 
doi={10.1109/DRC.2012.6257032}, 
ISSN={1548-3770},}

@INPROCEEDINGS{ZhangIEDM2012, 
author={Zhang, L and He, J. and Chan, M.}, 
booktitle={Electron Devices Meeting (IEDM), 2012 IEEE International}, 
title={A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors}, 
year={2012}, 
pages={6.8.1-6.8.4}, 
ISSN={0163-1918},}

@ARTICLE{VinayCMP2011, 
author={Saripalli, V. and Guangyu Sun and Mishra, A. and Yuan Xie and Datta, S. and Narayanan, V.}, 
journal={Emerging and Selected Topics in Circuits and Systems, IEEE Journal on}, 
title={Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors}, 
year={2011}, 
volume={1}, 
number={2}, 
pages={109-119}, 
doi={10.1109/JETCAS.2011.2158343}, 
ISSN={2156-3357},}

@ARTICLE{MichiganSRAM, 
author={Lee, Y. and others}, 
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, 
title={Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors {(HETTs)}}, 
year={2013}, 
month={Sept}, 
volume={21}, 
number={9}, 
pages={1632-1643}, 
keywords={Ge-Si alloys;SRAM chips;electronic engineering computing;elemental semiconductors;hardware description languages;integrated circuit design;low-power electronics;silicon;technology CAD (electronics);tunnel transistors;CMOS RO;MOSFET;ON-to-OFF current ratio;Si-SiGe;Verilog-A device model;asymmetric current flow;computer aided design tool;heterojunction tunneling transistor;increased Miller capacitance;low supply voltage;low-power circuit design analysis;low-voltage operation;power leakage reduction;ring oscillator;seven-transistor HETT-based SRAM cell topology;static random access memory operation;subthreshold swing limit;CMOS integrated circuits;Hardware design languages;Logic gates;MOSFETs;Random access memory;Tunneling;7T SRAM;heterojunction tunneling transistors (HETT);low-power;tunneling transistor}, 
doi={10.1109/TVLSI.2012.2213103}, 
ISSN={1063-8210},}

@INPROCEEDINGS{TrivediDAC2013, 
author={Trivedi, A.R. and Carlo, S. and Mukhopadhyay, S.}, 
booktitle={Design Automation Conference (DAC)}, 
title={Exploring Tunnel-{FET} for ultra low power analog applications: A case study on operational transconductance amplifier}, 
year={2013}, 
pages={1-6}, 
ISSN={0738-100X},}

@INPROCEEDINGS{VinayNanoarch2011, 
author={Saripalli, V. and Datta, S. and Narayanan, V. and Kulkarni, J.P.}, 
booktitle={Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on}, 
title={Variation-tolerant ultra low-power heterojunction tunnel {FET SRAM} design}, 
year={2011}, 
pages={45-52}, 
doi={10.1109/NANOARCH.2011.5941482},}

@INPROCEEDINGS{MattISQED2013, 
author={Cotter, M. and Huichu Liu and Datta, S. and Narayanan, V.}, 
booktitle={Quality Electronic Design (ISQED), 2013 14th International Symposium on}, 
title={Evaluation of tunnel {FET}-based flip-flop designs for low power, high performance applications}, 
year={2013}, 
pages={430-437}, 
doi={10.1109/ISQED.2013.6523647}, 
ISSN={1948-3287},}

@article{Ghibaudo2002,
title = "Electrical noise and {RTS fluctuations in advanced CMOS devices} ",
journal = "Microelectronics Reliability ",
volume = "42",
number = "4-5",
pages = "573 - 582",
year = "2002",
note = "",
issn = "0026-2714",
doi = "http://dx.doi.org/10.1016/S0026-2714(02)00025-2",
url = "http://www.sciencedirect.com/science/article/pii/S0026271402000252",
author = "G. Ghibaudo and T. Boutchacha"
}

@INPROCEEDINGS{KnitelIEDM2000, 
author={Knitel, M.J. and Woerlee, P.H. and Scholten, A.J. and Zegers-Van Duijnhoven, A.}, 
booktitle={Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International}, 
title={Impact of process scaling on 1/f noise in advanced {CMOS} technologies}, 
year={2000}, 
pages={463-466}, 
doi={10.1109/IEDM.2000.904356},}

@INPROCEEDINGS{AvciIEDM2013, 
author={Avci, U.E. and others}, 
booktitle={Electron Devices Meeting (IEDM), 2013 IEEE International}, 
title={Energy efficiency comparison of nanowire heterojunction {TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations}}, 
year={2013}, 
month={Dec}, 
pages={33.4.1-33.4.4}, 
keywords={CMOS integrated circuits;MOSFET;circuit simulation;elemental semiconductors;energy conservation;energy consumption;field effect transistors;gallium compounds;indium compounds;leakage currents;nanowires;silicon;CMOS;GaSb-InAs;MOSFET;N-TFET;P-TFET;Si;circuit simulation;energy consumption;energy efficiency;leakage current;mobile device battery life;nanowire;size 13 nm;subthreshold slope;threshold voltage;tunneling field effect transistor;CMOS integrated circuits;Capacitance;Delays;MOSFET;Performance evaluation;Silicon}, 
doi={10.1109/IEDM.2013.6724744},}

@ARTICLE{RahulTED2013, 
author={Pandey, R. and Rajamohanan, B. and Liu, H. and Narayanan, V. and Datta, S.}, 
journal={Electron Devices, IEEE Transactions on}, 
title={Electrical Noise in Heterojunction Interband Tunnel {FETs}}, 
year={2014}, 
volume={61}, 
number={2}, 
pages={552-560}, 
doi={10.1109/TED.2013.2293497}, 
ISSN={0018-9383},}

@ARTICLE{kuhn-variation, 
author={Kuhn, K.J. and others}, 
journal={Electron Devices, IEEE Transactions on}, 
title={Process Technology Variation}, 
year={2011}, 
month={Aug}, 
volume={58}, 
number={8}, 
pages={2197-2208}, 
keywords={CMOS memory circuits;SRAM chips;Moore law technology;circuit data;circuit variation measurement technique;front end variation source;intrinsic transistor variation performance;memory data;modern transistor technology;process variation management;size 32 nm;Arrays;Random access memory;Ring oscillators;Systematics;Transistors;$V_{rm ccmin}$;Complementary metaloxidesemiconductor (CMOS);static random access memory (SRAM);variation}, 
doi={10.1109/TED.2011.2121913}, 
ISSN={0018-9383},}

@INPROCEEDINGS{karthik-date14, 
author={Swaminathan, K. and others}, 
booktitle={Design Automation and Testing in Europe (DATE)}, 
title={Modeling steep slope devices: From circuits to architectures}, 
year={2014}, 
}

@INPROCEEDINGS{karthik-isca, 
author={Swaminathan, K. and Liu, H. and Sampson, J. and Narayanan, V. }, 
booktitle={International Symposium on Computer Architecture (ISCA)}, 
title={An examination of the Architecture and System-level Tradeoffs of Employing Steep Slope Devices in {3D CMPs} (to appear)}, 
year={2014}, 
}

@inproceedings{fabscalar,
  author = {Choudhary, N.K and others},
  biburl = {http://www.bibsonomy.org/bibtex/2ca948fbe506c1990392722d2e973d42f/dblp},
  booktitle = {International Symposium on Computer Architecture (ISCA)},
  isbn = {978-1-4503-0472-6},
  keywords = {dblp},
  pages = {11-22},
  publisher = {ACM},
  title = {FabScalar: composing synthesizable {RTL} designs of arbitrary cores within a canonical superscalar template.},
  year = 2011
}

@ARTICLE{lee-jssc2000,
    author = {Lee, T.H and Ali, H.},
    title = {Oscillator Phase Noise: A Tutorial},
    journal = {IEEE J. Solid-State Circuits},
    year = {2000},
    volume = {35},
    pages = {326--336}
}

@INPROCEEDINGS{hanada-3d, 
author={Hanada, T. and Sasaki, H. and Inoue, K. and Murakami, K.}, 
booktitle={3D Systems Integration Conference (3DIC)}, 
title={Performance evaluationa of {3D} stacked multi-core processors with temperature consideration}, 
year={2012}, 
month={Jan}, 
pages={1-5}, 
doi={10.1109/3DIC.2012.6263025},}

@INPROCEEDINGS{UCSDRectifier, 
author={Theilmann, P.T. and Presti, C.D. and Kelly, D. and Asbeck, P.M.}, 
booktitle={Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE}, 
title={Near zero turn-on voltage high-efficiency {UHF RFID rectifier in silicon-on-sapphire CMOS}}, 
year={2010}, 
month={May}, 
pages={105-108}, 
keywords={CMOS integrated circuits;radiofrequency identification;rectifiers;cross-coupled bridge topology;frequency 915 MHz;intrinsic near zero threshold devices;near zero input voltage;near zero turn-on voltage high-efficiency UHF RFID rectifier;silicon-on-sapphire CMOS;size 0.25 mum;Bridge circuits;CMOS technology;Power conversion;Radio frequency;Radiofrequency identification;Radiofrequency integrated circuits;Rectifiers;Topology;UHF measurements;Voltage;AC-DC power conversion;CMOS integrated circuits;RFID;power conversion efficiency (PCE);radio frequency rectifier;ultra-high frequency (UHF);wireless power transmission}, 
doi={10.1109/RFIC.2010.5477409}, 
ISSN={1529-2517},}

@INPROCEEDINGS{TFETCNN, 
author={Palit, I. and Hu, X.S. and Nahas, J. and Niemier, M.}, 
booktitle={ISLPED}, 
title={{TFET}-based cellular neural network architectures}, 
year={2013}, 
month={Sept}, 
pages={236-241}, 
keywords={CMOS digital integrated circuits;cellular neural nets;field effect transistors;low-power electronics;CMOS scaling trends;TFET devices;TFET-based CNN systems;TFET-based cellular neural network architectures;energy dissipation;low-power analog computing architecture;low-voltage device;resistor-based CNN;transfer functions;tunneling field effect transistor;Arrays;Capacitors;Image processing;Low voltage;SPICE;Transfer functions;Voltage control;CNN;Cellular Neural Networks;Low power;TFET;Tunneling Field Effect Transistor}, 
doi={10.1109/ISLPED.2013.6629301},}
